This invention relates to a decoder circuit for MOS memory of a redundant structure and in particular to such a decoder circuit intended for faster action.
A commonly used decoder circuit for MOS memory of a redundant structure is shown in FIG. 6, wherein No. 1 indicates MOS transistors for word line selection and address signals .phi..sub.A0 -.phi..sub.AN are connected to the individual gates, determining selection and deselection. A MOS transistor 2 for precharge is connected to the common drain of the MOS transistors 1 and a precharge signal .phi..sub.P is connected to the gate of the precharge MOS transistor 2. The gate of a MOS transistor 4 for driving the word line is also connected to the drain of the MOS transistors 1 through a transfer gate 3. A word line driving signal .phi..sub.3 is connected to the drain of the MOS transistor 4 and the signal .phi..sub.3 is transmitted to the word line 6 according to the control of the gate signal.
For the purpose of providing a decoder circuit suited for MOS memory of a redundant structure, there is inserted in the word line 6 an element 5 which is programmable by laser light or other external factors and is usually set in a transmissive condition. If a defect is detected in a memory cell connected to the word line 6, access to the defective memory cell can be prevented by shutting off the programmable element 5.
FIG. 7 is an action timing diagram of the decoder of FIG. 6, wherein .phi..sub.P is the precharge signal inputted at the gate of the precharge MOS transistor 2. During a precharge period, it precharges by the MOS transistor 2 both the node 7 which is the drain of the MOS transistors 1 and through the MOS transistor 3 the node 8 which is the gate of the word line driving MOS transistor 4. During an activation period, address signals .phi..sub.A0 -.phi..sub.AN are inputted for decoding and the nodes 7 and 8 of a deselected decoder circuit drop to ground potential, while the nodes 7 and 8 of a selected decoder circuit are maintained at high potentials. Next, the transfer signal .phi..sub.T drops and this sets the transfer gate 3 in an OFF position. Nodes 7 and 8 are thus cut off from each other and the driving signal .phi..sub.3 is inputted to the MOS transistor 4 and is outputted on the word line 6 of the selected decoder circuit.
In conventional decoder circuits, since the floating capacity C of the word line is generally large, significant signal delays occur due to the resistance of the programmable element 5 made of polisilicon, etc. It is generally difficult to reduce the resistance of this programmable element 5 and this, according to the conventional design shown in FIG. 6, has been the cause of large delays in the access time of memory elements.
It is therefore an object of this invention to provide a decoder circuit for MOS memory of a redundant structure intended for faster action, and it is achieved by changing the position at which the programmable element is connected.